1) Field of the Invention
The present invention relates generally to the fabrication of capacitors in a semiconductor memory device and more particularly to a method for fabricating a highly integrated semiconductor memory having a coaxial storage electrode for high reliability and large cell capacitance for memory cells.
2) Description of the Prior Art
The development of the semiconductor industry has always followed that of the Dynamic Random Access Memory (DRAM) technology in that the DRAM development has led in the use of the highest density technology elements capable of being produced in manufacturable quantities. The development of DRAM's in the 4 Megabit density range began to depart from the twenty year tradition of two-dimensional DRAM designs by the appearance of three-dimensional DRAM cell structures, most notable by the use of trench capacitors. Proposed designs for DRAM cells in 16 MB, 64 MB and high density range have also included the use of multi-plate or stacked storage capacitor cell designs. Although the use of stacked cell technology has rendered the processing of DRAMs more complex, such techniques continue to be used extensively.
The decrease in cell capacitance caused by reduced memory cell area is a serious obstacle to increasing packing density in dynamic random access memories (DRAMs). The problem of decreased cell capacitance must be solved to achieve higher packing density in semiconductor memory devices, since decreased cell capacitance degrades read-out capability and increases the soft error rate of memory cells as well as consumes excessive power during low-voltage operation by impeding device operation.
Generally, in a 64 MB DRAM having a 1.5 .mu.m.sup.2 memory cell area employing an ordinary two dimensional stacked capacitor cell, sufficient cell capacitance cannot be obtained even though a higher dielectric constant material, e.g., tantalum oxide (Ta.sub.2 O.sub.5), is used. Therefore, stacked capacitors having a three-dimensional structure have been suggested to improve cell capacitance. Such stacked capacitor include, for example double-stacked, fin-structured, cylindrical, spread-stacked, and box structured capacitors.
Since both outer and inner surfaces can be utilized as an effective capacitor area, the cylindrical structure is favorably suitable to the three-dimensional stacked capacitor, and is more particularly suited for an integrated memory cell which is 64 Mb or higher. Also, an improve stacked capacitor has recently been presented, where pillars or another inner cylinder is formed in the interior of the cylinder. Not only may both of the inner and outer surfaces of the cylinder be utilized as the effective capacitor area, but also the outer surface of the pillars or the inner cylinder formed in the interior of the cylinder. However, even more surface area and capacitance are required to achieve higher densities.
The following U.S. patents show related processes and capacitor structures: U.S. Pat. Nos. 5,399,518, Sim et at.; 5,403,767, Kim; 5,443,993, Park et at.; and 5,185,282, Lee et at. However, many of these methods require substantially more processing steps or/and planar structures which make the manufacturing process more complex and costly. Therefore, it is very desirable to develop processes that are as simple as possible.
There is a challenge to develop methods of manufacturing these capacitors that minimize the manufacturing costs and maximize the device yields. In particular, there is a challenge to develop a method which minimizes the number of photoresist masking operations and provides maximum process tolerance to maximize product yields. There is also a challenge to develop a coaxial capacitor which is easy to manufacture.